Degradation detector and method of detecting the aging of an integrated circuit

ABSTRACT

A degradation detector for an integrated circuit (IC), a method of detecting aging in an IC and an IC incorporating the degradation detector or the method. In one embodiment, the degradation detector includes: (1) an offline ring oscillator (RO) coupled to a power gate and a clock gate, (2) a frozen RO coupled to a clock gate, (3) an online RO and (4) an analyzer coupled to the offline RO, the frozen RO and the online RO and operable to place the degradation detector in a normal state in which the offline RO is disconnected from both the drive voltage source and the clock source, the frozen RO is connected to the drive voltage source but disconnected from the clock source and the online RO is connected to both the drive voltage source and the clock source.

CROSS-REFERENCE TO RELATED APPLICATION

This application is related to U.S. patent application Ser. No.13/723,139 filed by Kumar, et al., on Dec. 20, 2012, entitled“Quantifying Silicon Degradation in an Integrated Circuit,” jointlyassigned with this application and incorporated herein by reference.

TECHNICAL FIELD

This application is directed, in general, to integrated circuits (ICs)and, more specifically, to a system and method of detecting thedegradation of an IC over time.

BACKGROUND

Over the lifetime of an IC, various mechanisms result in the degradationof transistors, other components and interconnects of an IC. Hot-carrierinjection (HCI) occurs when charge carriers (electrons or holes),propelled by excess kinetic energy, stray into a nonconductive region ofa transistor, such as the gate dielectric of a metal-oxide semiconductorfield-effect transistor (MOSFET). Bias temperature instability (BTI)results from applying the same voltage to the control terminal of atransistor over time. Subsequent toggling of the transistor has toovercome the resulting voltage bias, slowing its switching speed. Chargetraps, which are pockets of conduction in a dielectric layer, can beformed over time and eventually cause the dielectric to break down andform a short circuit in a transistor. Electromigration occurs whenvoltage surges cause electrons in the interconnects to drift into thetransistors and remain there.

Degradation caused by HCI, BTI, charge-trap formation andelectromigration generally reduces the intrinsic speed of a transistorand the circuit in which the transistor is employed. In early stages ofdegradation, the circuit speed may be restored by increasing the voltageat which the circuit is driven. Later on, after the drive voltage hasbeen raised as far as possible, the frequency at which the circuit isdriven speeds should be reduced to accommodate the ever-decreasingcircuit speed. Eventually, however, the circuit will begin to behaveerratically and will eventually cease to function at all.

Degradation tends to become more predominant as new technologies haveallowed the sizes of transistors, other components and interconnects tobecome ever smaller. Various techniques have been devised to detect andcompensate for IC degradation. Those techniques have been more or lesssuccessful at increasing IC performance, extending IC life or predictingimpending IC failure.

SUMMARY

One aspect provides a degradation detector for an IC. In one embodiment,the degradation detector includes: (1) an offline ring oscillator (RO)coupled to a power gate and a clock gate, (2) a frozen RO coupled to aclock gate, (3) an online RO and (4) an analyzer coupled to the offlineRO, the frozen RO and the online RO and operable to place thedegradation detector in a normal state in which the offline RO isdisconnected from both the drive voltage source and the clock source,the frozen RO is connected to the drive voltage source but disconnectedfrom the clock source and the online RO is connected to both the drivevoltage source and the clock source.

Another aspect provides a method of detecting aging in an IC. In oneembodiment, the method includes: (1) entering a normal state, including:(1a) providing neither a drive voltage nor a clock signal to an offlineRO, (1b) providing the drive voltage but not the clock signal to afrozen RO and (1c) providing both the drive voltage and the clock signalto an online RO and (2) entering a detection state from the normalstate, the detection state including: (2a) providing both the drivevoltage and the clock signal to the offline RO, (2b) providing both thedrive voltage and the clock signal to the frozen RO and (2c) providingboth the drive voltage and the clock signal to the online RO.

Yet another aspect provides an IC. In one embodiment, the IC includes:(1) memory, (2) other integrated circuitry and (3) first and secondpower domains encompassing the memory and the other integratedcircuitry, the memory being associated with a first degradation detectorand the other integrated circuitry being associated with a seconddegradation detector. Each degradation detector includes: (3a) anoffline RO coupled to a power gate and a clock gate, (3b) a frozen ROcoupled to a clock gate, (3c) an online RO and (3d) an analyzer coupledto the offline RO, the frozen RO and the online RO and operable to placethe degradation detector in a normal state in which the offline RO isdisconnected from both the drive voltage source and the clock source,the frozen RO is connected to the drive voltage source but disconnectedfrom the clock source and the online RO is connected to both the drivevoltage source and the clock source, inverters in the offline RO, thefrozen RO and the online RO of the first degradation detector being of asame architecture as the memory, inverters in the offline RO, the frozenRO and the online RO of the second degradation detector being of a samearchitecture as the other integrated circuitry.

BRIEF DESCRIPTION

Reference is now made to the following descriptions taken in conjunctionwith the accompanying drawings, in which:

FIG. 1 is a high-level block diagram of one example of an IC havingmultiple voltage and/or clock domains and various types of integratedcircuitry located thereon;

FIG. 2 is a block diagram of one embodiment of a degradation detectorfor detecting the aging of integrated circuitry; and

FIG. 3 is a flow diagram of one embodiment of a method of detecting theaging of integrated circuitry.

DETAILED DESCRIPTION

As stated above, various techniques have been devised to detect andcompensate for IC degradation. The techniques have mostly centeredaround using an RO as a speedometer. As those skilled in the pertinentart are familiar, an RO is constructed by series-coupling an odd numberof inverters in a loop. An input state of one of the inverters istoggled, causing a cascading state change in each subsequent inverterthat resonates around the RO at a frequency that is largely a functionof the speeds of the transistors making up the inverters. If the RO isworking properly, it will provide an output frequency that favorablycompares with a stored reference number. If the comparison is favorable,decreases in drive voltage, increases in clock frequency, or somecombination thereof, may be in order, perhaps until the comparisonbecomes unfavorable. If the output frequency is less than the reference,the RO has degraded to some degree, and increases in drive voltage,perhaps leading to eventual decreases in clock speed, may be in order.

Some of the above-referenced techniques are directed to detecting BTI.BTI is especially difficult to detect, because it is exhibited onlybriefly after the voltage that has been applied to a control terminalover time has been interrupted. To detect the barely-detectible, onetechnique employs dual ROs to generate a beat frequency: one RO that hasbeen subjected to BTI, and another RO that has not (see, Keane, et al.,“Transistor Aging,” IEEE Spectrum, http://spectrum.ieee.org/semiconductors/processors/transistor-aging, posted 25 Apr. 2011).Nevertheless, a comprehensive technique for accurately detecting thecauses of transistor degradation has been elusive.

It is realized herein that transistor degradation occurs as a result ofuse, and degradation is most accurately measured when the referenceagainst which it is measured is appropriate. It is therefore realizedthat the reference used to gauge the performance of an RO should be areference RO instead of a stored reference number and that the referenceRO should be rendered inoperable when detection is not being performedso the reference RO can be preserved to be close to its originallyfabricated state.

It is yet further realized herein that, while the output frequency an ROgenerates is a trusted indicator of degradation, the duty cycle of thefrequency also helps in diagnosing the type of degradation taking place.It is still further realized herein that known boundary scan techniquescan be employed to initiate and read out the results of degradationdetection.

It is yet still further realized herein that a degradation detector canbe made more accurate when its inverters are of the same architecture asthe integrated circuitry with which it is associated. For example, adegradation detector for dynamic random-access memory (DRAM) should useDRAM cells in its inverters. Likewise, a degradation detector for afield-programmable gate array (FPGA) should use programmable gates inits inverters.

It is still yet further realized that degradation detectors mayadvantageously be placed in multiple voltage domains, multiple clockdomains, or both, in an IC having multiple domains, since degradationtends to occur at different rates, depending upon drive voltage, clockrate and the technologies employed to fabricate the various IC domains.

Described herein are various embodiments of a degradation detector and amethod of detecting the aging of integrated circuitry. The variousembodiments take advantage of one or more of the realizations describedabove.

FIG. 1 is a high-level block diagram of one example of an IC 100 havingmultiple voltage and/or clock domains. Illustrated are a first voltageand/or clock domain 110 and a second voltage and/or clock domain 120.The first voltage and/or clock domain 110 is illustrated as including amemory 112, a processor 114 and a logic array 116. The memory 112 may beDRAM, static random-access memory (SRAM), read-only memory (ROM),programmable ROM (PROM) or any other conventional or later-developedmemory type. The processor 114 may be a microprocessor, microcontroller,parallel processor, special-purpose (e.g., graphics) processor or anyother conventional or later-developed processor type. The logic array116 be a field-programmable gate array (FPGA), a programmable logicarray (PLA) a programmable array logic (PAL) or any other convention orlater-developed type of logic array.

The second voltage and/or clock domain 120 is illustrated as includingother integrated circuitry 122 of unspecified type, hybrid(analog/digital) circuitry 124 and input/output (I/O) circuitry 126. Theother integrated circuitry 122 may be any circuitry that can beintegrated onto a common substrate either now or in the future. Thehybrid circuitry 124 may include digital-to-analog converters (DACs),analog-to-digital converters (DCAs) or analog circuitry that can beintegrated onto a common substrate either now or in the future. Theinput/output (I/O) circuitry 126, may include drivers, receivers,latches, buffers and serializers/deserializers (SERDESs) of variousconventional or later-developed types.

Each of the memory 112, the processor 114, the logic array 116, theother integrated circuitry 122, the hybrid circuitry 124 and the I/Ocircuitry 126 has associated with it a respective degradation detector113, 115, 117, 123, 125, 127. In the illustrated embodiment, ROs (notshown) in each degradation detector 113, 115, 117, 123, 125, 127 employinverters (not shown) that are of the same type as the circuitry of theportion of the IC in which each degradation detector 113, 115, 117, 123,125, 127 lies (i.e. the memory 112, the processor 114, the logic array116, the other integrated circuitry 122, the hybrid circuitry 124 andthe I/O circuitry 126, respectively). For example, the ROs (not shown)of the degradation detector 113 employ memory cells, and the ROs (notshown) of the I/O circuitry 122 employ drivers or receivers.

Irrespective of the type of circuitry constituting the inverters in theROs of the degradation detectors 113, 115, 117, 123, 125, 127, theoverall architecture of the degradation detectors 113, 115, 117, 123,125, 127 may remain the same. FIG. 2 is a block diagram of oneembodiment of a degradation detector 210 for detecting the aging ofintegrated circuitry. The illustrated embodiment of the degradationdetector 210 includes one or more “offline” ROs 220, one or more“frozen” ROs 230 and one or more “aging” ROs 240. In the illustratedembodiment, the one or more “offline” ROs 220, the one or more “frozen”ROs 230 and the one or more “aging” ROs 240 are of the same architectureand fabricated using the same types and sizes of transistor such thatthey ideally operate identically. In the illustrated embodiment, the oneor more “offline” ROs 220, the one or more “frozen” ROs 230 and the oneor more “aging” ROs 240 contain inverters (not shown) having the samearchitecture as the integrated circuitry with which it is associated.For example, the degradation detector 115 uses gates that are of thesame architecture as those used in the processor 114.

It is possible, however, that fabrication variations may cause the oneor more “offline” ROs 220, the one or more “frozen” ROs 230 and the oneor more “aging” ROs 240 to oscillate differently in the absence ofaging. Accordingly, some embodiments of the degradation detector 210employ fuses or other compensating mechanisms to alter the operation ofthe one or more “offline” ROs 220, the one or more “frozen” ROs 230 andthe one or more “aging” ROs 240 or indicate how the results of theiroperation should be compensated to become valid.

The one or more offline ROs 220, the one or more frozen ROs 230 and theone or more online ROs 240 are coupled to respective output counters222, 232, 242 and duty cycle detectors 224, 234, 244 at outputs thereof.Only one counter 222, 232, 242 and one duty cycle detector 224, 234, 244is shown for each of the ROs 220, 230, 240; however, those skilled inthe pertinent art will understand that other embodiments may have morecounters 222, 232, 242 and/or duty cycle detectors 224, 234, 244. Thecounters 222, 232, 242 are operable to contain numbers that depend uponthe output frequency of their corresponding ROs 220, 230, 240. The dutycycle detectors 224, 234, 244 are operable to contain numbers thatdepend upon the duty cycles of the output of their corresponding ROs220, 230, 240. “Duty cycle” is defined for purposes of this disclosureas the proportion (e.g., percentage) of time an RO output is in aparticular logic state, e.g., a logic one state. An ideal binary RO thathas suffered no degradation should have a duty cycle of 0.5, or 50%,meaning that its output spends exactly as much time in a logic one stateas it does in a logic zero state.

An analyzer 250 is coupled to the counters 222, 232, 242 and the dutycycle detectors 224, 234, 244 and is operable to reset and read thecounters 222, 232, 242 and the duty cycle detectors 224, 234, 244 andopen or close the power gate 226 and the clock gates 236. Although FIG.2 depicts the analyzer 250 as a block of circuitry, alternativeembodiments embody the analyzer as software or firmware executing on aprocessor or controller and communicating with the gates 226, 228, 236,the counters 222, 232, 242 and the duty cycle detectors 224, 234, 244remotely, perhaps using a test scanning technique, such as that devisedby the Joint Test Action Group (JTAG), in which registers would beemployed to open and close the gates 226, 228, 236 and reset and readthe counters 222, 232, 242 and the duty cycle detectors 224, 234, 244.

As implied above, the one or more offline ROs 220 are provided with botha power gate 226 and a clock gate 228. The power gate 226 is operable todisconnect the one or more offline ROs 220 from a drive voltage source260, and the clock gate 228 is operable to disconnect the one or moreoffline ROs 220 from a clock source 270, rendering the one or moreoffline ROs 220 inoperable, hence the term, “offline.”

In contrast, the one or more frozen ROs 230 are coupled to the drivevoltage source 260 persistently, no power gate is provided to disconnectthe one or more clock-gated ROs 220. However, the one or more frozen ROs230 are provided with a clock gate 236. The clock gate 236 is operableto disconnect the one or more frozen ROs 230 from the clock source 270,which places the one or more frozen ROs 230 in a “frozen” state, definedas a state in which transistors in the one or more frozen ROs 230initially assume logic one and logic zero levels, but clock-driven logictransitions (including oscillations in the one or more frozen ROs 230)cannot thereafter occur. The initially-assumed logic one and logic zerolevels remain in place, hence the term, “frozen.”

In further contrast, the one or more online ROs 240 are coupled to boththe drive voltage source 260 and the clock source 270 persistently, nopower gate or clock gate is provided to disconnect the one or moreclock-gated ROs 220. Consequently, the one or more online ROs 240oscillate as the IC (100 of FIG. 1) as a whole operates, aging as timemarches on, hence the term, “online.”

The operation of the degradation detector 210 embodiment of FIG. 2 willnow be described. The degradation detector 210 has two states: a normalstate and a detection state. It is expected that the degradationdetector 210 will usually operate in the normal state, perhaps justshort of 100% of the time and that the detection state will be assumedonly occasionally and only as long as necessary to gather dataindicating degradation. Of course, no practical limit exists to theamount of time that may be spent operating in the detection state.However, those skilled in the pertinent art will come to understand thatoperating in the detection state is likely to age the one or moreoffline ROs 220, mitigate BTI in the one or more frozen ROs 230 andreduce the contrast in operation among the one or more offline ROs 220,the one or more frozen ROs 230 and the one or more online ROs 240.

In the normal state, an analyzer 250 coupled to the counters 222, 232,242 and the duty cycle detectors 224, 234, 244 closes the power gate 226and the clock gates 228, 236. Thus, the one or more offline ROs 220 aredisconnected from both the drive voltage source 260 and the clock source270 and are inoperable. In contrast, the one or more frozen ROs 230 aredisconnected from only the clock source 280, causing them to be placedin a frozen state in which logic one and logic zero levels, onceinitially entered, are maintained persistently in the transistors of theinverters of the one or more frozen ROs 230.

In further contrast, the one or more online ROs 240 remain connected tothe drive voltage source 260 and the clock source 270 and thus operateand oscillate at their inherent frequency, which, assuming a constantdrive voltage, typically declines as the one or more online ROs 240 age.

In the detection state, the analyzer 250 opens the power gate 226 andthe clock gates 228, 236. This turns on the one or more offline ROs 220,causing them to begin oscillating and further causes the one or morefrozen ROs 230 to begin oscillating. The one or more online ROs 240continue operating and oscillating as before in the normal state.

To begin detection, the counters 222, 232, 242 and the duty cycledetectors 224, 234, 244 are reset and begin to count and accrue dutycycle statistics. Over some test interval, which may be selected basedon a host of factors that depend upon a particular IC and perhaps itsenvironment, the numbers in the counters 222, 232, 242 and the dutycycle detectors 224, 234, 244 are read and analyzed to determinedegradation.

If the IC is relatively young, the numbers read from the counters 222,232, 242 should be close to (e.g., within 1% of) one another, and thenumbers read from the duty cycle detectors 224, 234, 244 should likewisebe similar and very close to 0.5.

Assuming that some time has passed (e.g., a few years), it may beobserved that the numbers read from the counter 222 may substantiallyexceed (e.g., be more than 105% of) the numbers read from the counters232, 242. Degradation may be setting in, and drive voltage to the IC mayneed to be increased to compensate for it, or the clock rate may need tobe decreased to accommodate it.

Additional or alternative analyses are possible. For example, the numberread from the counter 222 may substantially exceed the number read fromthe counter 242, or the number read from the duty cycle detector 224 maydiffer substantially from the number read from the duty cycle detector244, providing at least some indication that aging due to HCI,charge-trap formation or electromigration has occurred.

The number read from the counter 222 may substantially exceed the numberread from the counter 232, indicating that aging due to BTI hasoccurred. Additionally, deviation in the number read from the duty cycledetector 234 may indicate whether the BTI is positive or negative. Inone embodiment, at least two ROs are included in the frozen ROs 230. OneRO is fabricated such that it is biased to provide maximum positive BTIstress. The other RO is fabricated such that it is biased to providemaximum negative BTI stress. This arrangement may provide additionaldata regarding aging.

If, for example, the degradation detector in question happens to be thedegradation detector 113, a legitimate concern may arise that certainportions of the associated memory 112 that tend not to change stateoften (e.g., those storing instructions or constants) may be in dangerof losing their ability to respond to attempted writes at an acceptablespeed. Mitigating the concern may involve exercising at least thoseportions of the memory 112 by toggling them, moving more persistent datato other portions of the memory 112 or issuing a warning of some sort.

Toward the end of the life of the IC, the numbers read from the counters222, 232, 242 may be quite disparate from one another and/or the numbersread from the duty cycle detectors 234, 244 may vary substantially fromthe number read from the duty cycle detector 224 or an ideal 0.5.Assuming that the drive voltage of the IC has already been increased toa maximum, and clock speeds have already been throttled back, ratherextreme actions may be taken, such as issuing a strong warning ordisabling all or portions of the IC, perhaps delegating the functionsthat the IC performs to other ICs.

Those skilled in the pertinent art will see broad variety of ways notonly to analyze and interpret the numbers read out from the counters222, 232, 242 and the duty cycle detectors 224, 234, 244, but also toact in response to the analysis and interpretation. Those skilled in thepertinent art will also understand that circuits other than counters andduty cycle detectors may be coupled to the ROs 220, 230, 240 to provideadditional data regarding their operation. For example, Kumar (citedabove and incorporated herein by reference) is replete with informationregarding how IC degradation may be quantified. Those skilled in thepertinent art will readily be able to adapt the teachings in Kumar tothe degradation detector and method introduced herein.

FIG. 3 is a flow diagram of one embodiment of a method of detecting theaging of integrated circuitry. The method begins in a start step 310.Steps 320, 330, 340 pertain to a normal state of operation. In the step320, neither a drive voltage nor a clock signal is provided to anoffline RO. In the step 330, the drive voltage is provided to a frozenRO, but not the clock signal. In the step 340, both the drive voltageand the clock signal are provided to an online RO. Steps 350, 360, 370pertain to a detection state. Upon entering the detection state,counters and duty cycle detectors associated with the offline, frozenand online ROs detectors are reset and begin to gather data. In the step350, both the drive voltage and the clock signal are provided to theoffline RO. In the step 360, both the drive voltage and the clock signalare provided to the frozen RO. In the step 370, both the drive voltageand the clock signal are provided to the online RO. After the passage ofsome time, numbers from the counters and the duty cycle detectors areanalyzed to determine whether or not IC aging has taken place. If suchaging has taken place, a variety of mitigating or warning steps may betaken. The method ends in an end step 380.

Those skilled in the art to which this application relates willappreciate that other and further additions, deletions, substitutionsand modifications may be made to the described embodiments.

What is claimed is:
 1. A degradation detector for an integrated circuit,comprising: an offline ring oscillator coupled to a drive voltage sourcevia a power gate and a clock source via a first clock gate; a frozenring oscillator coupled to a second clock gate; an online ringoscillator persistently coupled to said drive voltage source and saidclock source; and an analyzer coupled to said offline ring oscillator,said frozen ring oscillator and said online ring oscillator and operableto place said degradation detector in a normal state in which saidoffline ring oscillator is disconnected from both said drive voltagesource and said clock source, said frozen ring oscillator is connectedto said drive voltage source but disconnected from said clock source andsaid online ring oscillator is connected to both said drive voltagesource and said clock source.
 2. The degradation detector as recited inclaim 1 wherein said degradation detector is associated with otherintegrated circuitry, inverters in said offline ring oscillator, saidfrozen ring oscillator and said online ring oscillator being of a samearchitecture as said other integrated circuitry.
 3. The degradationdetector as recited in claim 1 wherein said analyzer is further operableto place said degradation detector in a detection state in which saidoffline ring oscillator, said frozen ring oscillator and said onlinering oscillator are connected to both said drive voltage source and saidclock source.
 4. The degradation detector as recited in claim 1 furthercomprising counters coupled to said offline ring oscillator, said frozenring oscillator and said online ring oscillator and operable to providenumbers to said analyzer.
 5. The degradation detector as recited inclaim 1 further comprising duty cycle detectors coupled to said offlinering oscillator, said frozen ring oscillator and said online ringoscillator and operable to provide numbers to said analyzer.
 6. Thedegradation detector as recited in claim 1 wherein said frozen ringoscillator is biased to provide maximum positive BTI stress and saiddegradation detector further comprises another frozen ring oscillatorbiased to provide maximum negative BTI stress.
 7. The degradationdetector as recited in claim 1 wherein said analyzer is further operableto provide a signal indicating an aging of said integrated circuit.
 8. Amethod of detecting aging in an integrated circuit, comprising: enteringa normal state, including: providing neither a drive voltage nor a clocksignal to an offline ring oscillator, providing said drive voltage butnot said clock signal to a frozen ring oscillator, and providing bothsaid drive voltage and said clock signal to an online ring oscillator;and entering a detection state from said normal state, said detectionstate including: providing both said drive voltage and said clock signalto said offline ring oscillator, providing both said drive voltage andsaid clock signal to said frozen ring oscillator, and providing bothsaid drive voltage and said clock signal to said online ring oscillator.9. The method as recited in claim 8 wherein said offline ringoscillator, said frozen ring oscillator and said online ring oscillatorare associated with other integrated circuitry, inverters in saidoffline ring oscillator, said frozen ring oscillator and said onlinering oscillator being of a same architecture as said other integratedcircuitry.
 10. The method as recited in claim 8 further comprisingproviding numbers from counters coupled to said offline ring oscillator,said frozen ring oscillator and said online ring oscillator in saiddetection state.
 11. The method as recited in claim 8 further comprisingproviding numbers from duty cycle detectors coupled to said offline ringoscillator, said frozen ring oscillator and said online ring oscillatorin said detection state.
 12. The method as recited in claim 8 whereinsaid frozen ring oscillator is biased to provide maximum positive BTIstress and said degradation detector further comprises another frozenring oscillator biased to provide maximum negative BTI stress.
 13. Themethod as recited in claim 8 further comprising providing a signalindicating an aging of said integrated circuit.
 14. An integratedcircuit, comprising: memory; other integrated circuitry; and first andsecond power domains encompassing said memory and said other integratedcircuitry, said memory being associated with a first degradationdetector and said other integrated circuitry being associated with asecond degradation detector, each said degradation detector including:an offline ring oscillator coupled to a drive voltage source via a powergate and a clock source via a first clock gate, a frozen ring oscillatorcoupled to a second clock gate, an online ring oscillator oscillatorpersistently coupled to said drive voltage source and said clock source,and an analyzer coupled to said offline ring oscillator, said frozenring oscillator and said online ring oscillator and operable to placesaid degradation detector in a normal state in which said offline ringoscillator is disconnected from both said drive voltage source and saidclock source, said frozen ring oscillator is connected to said drivevoltage source but disconnected from said clock source and said onlinering oscillator is connected to both said drive voltage source and saidclock source, inverters in said offline ring oscillator, said frozenring oscillator and said online ring oscillator of said firstdegradation detector being of a same architecture as said memory,inverters in said offline ring oscillator, said frozen ring oscillatorand said online ring oscillator of said second degradation detectorbeing of a same architecture as said other integrated circuitry.
 15. Theintegrated circuit as recited in claim 14 further comprising first andsecond clock domains.
 16. The integrated circuit as recited in claim 14wherein said analyzer is further operable to place said degradationdetector in a detection state in which said offline ring oscillator,said frozen ring oscillator and said online ring oscillator areconnected to both said drive voltage source and said clock source. 17.The integrated circuit as recited in claim 14 wherein said degradationdetector further comprising counters coupled to said offline ringoscillator, said frozen ring oscillator and said online ring oscillatorand operable to provide numbers to said analyzer.
 18. The integratedcircuit as recited in claim 14 wherein said degradation detector furthercomprising duty cycle detectors coupled to said offline ring oscillator,said frozen ring oscillator and said online ring oscillator and operableto provide numbers to said analyzer.
 19. The integrated circuit asrecited in claim 14 wherein said frozen ring oscillator is biased toprovide maximum positive BTI stress and said degradation detectorfurther comprises another frozen ring oscillator biased to providemaximum negative BTI stress.
 20. The integrated circuit as recited inclaim 14 wherein said analyzer is further operable to provide a signalindicating an aging of said integrated circuit.